I was born in Albufeira, Portugal in March 1979. In 1997 I've completed the elementary studies in Escola EB2+3/S Dr. João de Brito Camacho in Almodôvar, Portugal. In 2003, I've received the Licenciatura (5 years degree) in Engenharia de Sistemas e Computação from University of Algarve in Faro, Portugal. Since January 2004, I've been working as a researcher in project CHIADO in the Ualg Informatics Laboratory at University of Algarve, under supervision of professor João Cardoso. Currently, I'm also a MSc. student at Instituto Superior Técnico - Tecnical University of Lisbon, Portugal.
My research interests include:
Currently, I'm working in project CHIADO (POSI/CHS/48018/2002) [*]:
Reconfigurable computing (RC) has already confirmed a significant potential for accelerating certain general-purpose computing tasks. Since RC systems are capable to provide a mix of flexibility, high-performance, and low power consumption (when compared to microprocessors and DSPs) their use is increasing. As RC is based on hardware foundations, it inherited its design difficulties. The methods that have been used for the realization of the most successful applications of RC require user's hardware expertise. Today's RC devices, with millions of logic gates, distributed memories and embedded multipliers, are capable to accommodate complex algorithms. Thus, one of the most challenging issues is the methodology to efficiently and automatically map computations (described in software programming languages) to these systems. Moreover, the compiler performance must not be significantly slower than software compilation to a generic processor in order to permit rapid development and evaluation of different high-level decisions (e.g., hardware/software partitioning), both important to deal with time-to-market pressures.
Since the execution on RC systems can be divided in sequential stages (e.g., fetch, configure, and compute) it is important to find, from the input algorithm, the set of configurations that both produces feasible implementations (considering the available number of resources) and minimizes the overall performance. To minimize the performance it is essential to consider the overlapping of the stages related to different configurations. Based on our previous work on temporal partitioning and on the framework already existent, we propose to R&D techniques to map efficiently complex applications to RC systems also considering this form of pipelining. The work includes high-level estimations (resources needed and latency) from the original algorithm and including the impact of some transformations supported by the compiler (partial/full loop unrolling).
In order to provide full support for the design compilation, the work will also include the R&D of module-generators to produce the specific components mainly required to access the memories and to perform the primitive operations used in the Java subset. In parallel to the R&D of mapping methods, two practical benchmarks will be implemented with a traditional design flow in a commercial RC board in order to find efficient hardware techniques and to provide a final evaluation of the results obtained using the compiler.
[*] Cardoso, João M P., "Projecto CHIADO". in Proceedings of Jornadas Sobre Computação Reconfigurável (REC2005), Faro, Portugal, Feb 2005.
 Rodrigues, Rui M and Cardoso, João M P., "A Test Infrastructure for Compilers Targeting FPGAs". in Procedings of International Workshop on Applied Reconfigurable Computing (ARC 2005). Carvoeiro, Algarve, Portugal, Feb 2005.
 Rodrigues, Rui M and Cardoso, João M P., "Pipelining Sequences of Loops: A First Example". in Procedings of International Workshop on Applied Reconfigurable Computing (ARC 2005). Carvoeiro, Algarve, Portugal, Feb 2005.
 Rodrigues, Rui M and Cardoso, João M P., "An Infrastructure To Functionally Test Designs Generated By Compilers Targeting FPGAs". in Proceding of DATE2005. Munich, Germany, Mar 2005.
Friends at Ualg:
Email: rrodrigues + ualg * pt
Phone: +351 289800900 (ext: 7743)
UAlg - Informatics Laboratory (room 2.58)
Departamento de Engenharia Electrónica e Informática
Faculdade de Ciências e Tecnologia
Universidade do Algarve
Campus de Gambelas
8005 - 139 FARO