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[Thesis] [Edited
Volumes] [Book Chapters] [Journal Papers] [Symposium and
Conference Papers] [National Conference Papers]
[Patents]
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Thesis |
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João M. P. Cardoso, “Compilation of JavaÔ
Algorithms onto Reconfigurable Computing Systems with Exploitation of
Operation-Level Parallelism,” Ph.D. Thesis (in Portuguese), IST,
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João M. P. Cardoso, “Co-Synthesis of Embedded Systems onto
Gate-Array Technology,” Master Thesis (in Portuguese), IST,
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Edited Volumes, Special Issues |
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João M. P. Cardoso, and George Constantinides (guest eds.), Special
Issue: Applied Reconfigurable Computing, International Journal of
Electronics (IJE), Taylor & Francis, 2006.
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João M. P. Cardoso (editor), Proceedings of the International Workshop on
Applied Reconfigurable Computing (ARC2005), Algarve, Portugal, 22-23
February, 2005, IADIS Press, ISBN 972-99353-8-6.
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João M. P. Cardoso, and José
Carlos Alves (eds.), Actas das Jornadas sobre Sistemas
Reconfiguráveis (REC2005), Universidade do Algarve, Portugal, 21
February 2005, ISBN 972-9341-41-9.
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João M. P. Cardoso, and Markus Weinhardt, “Compilation and Temporal Partitioning for a Coarse-grain
Reconfigurable Architecture,” Chapter 9 in New Algorithms, Architectures, and Applications for Reconfigurable
Computing, Patrick Lysaght and Wolfgang Rosenstiel (eds.), Springer, April
2005. pp. 105-115. ISBN
1-4020-3127-0.
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Journal
Papers |
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João M. P.
Cardoso, and Horácio C. Neto, “Compilation for FPGA-Based Reconfigurable
Hardware,” IEEE Design & Test of Computers Magazine, March/April, 2003, vol. 20, no.2, pp.
65-75.
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João M. P. Cardoso, “On Combining Temporal Partitioning and Sharing of
Functional Units in Compilation for Reconfigurable Architectures,” in IEEE Transactions on Computers, Vol. 52,
No. 10, October 2003, pp. 1362-1375.
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João M. P. Cardoso, and Mário P. Véstias, “Architectures and
Compilation Techniques to Support Reconfigurable Computing,” Crossroads,
the Association for Computing Machinery (ACM) Student Magazine, topic: Computer
Architectures, Spring 1999, Issue 5.3, ACM Press, New York, USA, pp. 15-22.
Version online at: http://www.acm.org/crossroads/xrds5-3/rcconcept.html
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João M. P. Cardoso, Pedro Diniz, and Markus Weinhardt, “Compilation
for Reconfigurable Computing Platforms: Comments on Techniques and Current
Status,” submitted to the ACM Computing Surveys (September 2002).
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Papers in Refereed International Symposiums, Conferences and
Workshops |
|
2006 |
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João M. P.
Cardoso, João M. Fernandes, and Miguel Monteiro, “Adding Aspect-Oriented Features to
MATLAB,” in SPLAT! 2006, Software
Engineering Properties of Languages and Aspect Technologies, A workshop
affiliated with AOSD 2006, March 21, 2006.
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Jorge
Silva, Marcio M. Fernandes, Vanderlei Bonato, Ricardo Menotti, João M. P.
Cardoso, and Eduardo Marques, “Using Mobile Robotics to Teach Reconfigurable
Computing,” in The 1st International
Workshop on Reconfigurable Computing Education (RC-Education), March 1,
2006, Karlsruhe, Germany.
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2005 |
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João M. P.
Cardoso, “On
Estimations for Compiling Software to FPGA-based Systems,” in IEEE 16th International Conference on
Application-specific Systems, Architectures and Processors (ASAP’05),
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João M. P.
Cardoso, “New
Challenges in Computer Science Education,” in 10th ACM Annual Conference on Innovation and Technology in Computer
Science Education (ITiCSE’05), Universidade Nova de Lisboa, Lisbon,
Portugal, June 27-29, 2005, ACM Press, pp. 203-207.
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Ricardo
Ferreira, João M. P. Cardoso, Andre Toledo, and Horácio C. Neto, “Data-driven Regular Reconfigurable Arrays: Design
Space Exploration and Mapping,” in Embedded
Computer Systems: Architectures, Modeling, and Simulation 5th International
Workshop, Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis
Vassiliadis (Eds.), SAMOS 2005, Samos, Greece, July 18-20, 2005, LNCS 3553
Springer, pp. 41-50.
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João M. P.
Cardoso, “Data-driven array
architectures: a rebirth?,” in SPIE
Microtechnologies for the New Millennium 2005 Symposium, Seville, Spain,
May 9-11, 2005, SPIE Vol. 5837, pp. 479-490.
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João M. P.
Cardoso, “CHIADO: compilation of
high-level computationally intensive algorithms to dynamically reconfigurable
computing systems,” in SPIE
Microtechnologies for the New Millennium 2005 Symposium,
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João M. P.
Cardoso, “Dynamic
Loop Pipelining in Data-Driven Architectures,” in Proc. of the ACM International Conference on Computing Frontiers
(CF’05), Ischia, Italy, 4-6 May 2005, ACM Press, pp. 106-115.
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Rui
Rodrigues, and João M. P. Cardoso, “A Test Infrastructure for Compilers Targeting
FPGAs,” in International Workshop
on Applied Reconfigurable Computing (ARC2005), held in conjunction with IADIS International Conference Applied
Computing 2005,
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Rui
Rodrigues, and João M. P. Cardoso, “Pipelining Sequences of Loops: A First Example,”
in International Workshop on Applied
Reconfigurable Computing (ARC2005), held in conjunction with IADIS International Conference Applied
Computing 2005,
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Rui
Rodrigues, and João M. P. Cardoso, “An
Infrastructure to Functionally Test Designs Generated by Compilers Targeting
FPGAs,” Interactive Presentation at the Design,
Automation and Test in Europe Conference (DATE’05),
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2004 |
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Ricardo Ferreira, João M. P. Cardoso, and Horácio C. Neto, “An Environment for Exploring
Data-Driven Architectures,” in 14th
International Conference on Field Programmable Logic and Applications (FPL’04),
Antwerp, Belgium, August 30 - September 1, 2004, LNCS 3203, Springer-Verlag, Jürgen Becker, Marco
Platzner, Serge Vernalde (eds.), August 2004, pp. 1022-1026 .
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Vanderlei Bonato, Adriano K. Sanches, Márcio Fernandes, João M. P.
Cardoso, Eduardo Simões, and Eduardo Marques,
“A Real Time Gesture Recognition System
for Mobile Robots,” In International Conference on Informatics in Control, Automation, and
Robotics (ICINCO’04), August 25-28, Setúbal, Portugal, 2004, INSTICC, pp. 207-214.
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João M. P. Cardoso, and Pedro C. Diniz, “Modeling
Loop Unrolling: Approaches and Open Issues,” in International Workshop on Systems, Architectures, MOdeling, and
Simulation (SAMOS IV),
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João M. P. Cardoso, “Self Loop
Pipelining and Reconfigurable Dataflow Arrays,” in International Workshop on Systems, Architectures, MOdeling, and
Simulation (SAMOS IV),
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Gil Moreira, João M. P. Cardoso, “Easy Development of GUIs Using XML
and Java Reflection,” in Proc. of the
IADIS International Conference Applied Computing,
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2003 |
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João M. P. Cardoso, “Loop Dissevering: A Technique
for Temporally Partitioning Loops in Dynamically Reconfigurable Computing
Platforms,” in 10th
Reconfigurable Architectures Workshop (RAW 2003), Nice,
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João M. P. Cardoso, and Markus Weinhardt, “From C
Programs to the Configure-Execute Model,” in Proc. of the Design, Automation and Test in Europe Conference (DATE’03),
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R. A. Gonçalves, P.A. Moraes, J. M. P. Cardoso, D. F. Wolf, M. M.
Fernandes, R. A. F. Romero, E. Marques, “ARCHITECT-R: A System for
Reconfigurable Robots Design,” in ACM
Symposium on Applied Computing (SAC 2003), March 9-12,
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2002 |
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João M. P. Cardoso, and Markus Weinhardt, “XPP-VC: A C Compiler with
Temporal Partitioning for the PACT-XPP Architecture,” in 12th
International Conference on Field Programmable Logic and Applications (FPL'02),
Montpellier, France, Sept. 2-4, 2002, Proceedings LNCS (Lecture Notes on
Computer Science) 2438, Springer Verlag, M. Glesner, P. Zipf, M.
Renovell (Eds.), August 2003, pp. 864-874.
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João M. P. Cardoso, and Markus Weinhardt, “Fast and Guaranteed C
Compilation onto the PACT-XPP Reconfigurable Computing Platform,” In Proc. of the IEEE 10th Symposium
on Field-Programmable Custom Computing Machines (FCCM'02),
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2001 |
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João M. P. Cardoso, “A Novel Algorithm Combining
Temporal Partitioning and Sharing of Functional Units,” In IEEE 9th
Symposium on Field-Programmable Custom Computing Machines (FCCM'01), Rohnert Park, California, USA, April 30 – May
2, 2001, IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 31-40. [Presentation
Slides in Power Point]
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João M. P. Cardoso, and Horácio C. Neto, “Compilation Increasing the
Scheduling Scope for Multi-Memory-FPGA-based Custom Computing Machines,”
In 11th International Conference on Field Programmable Logic and
Applications (FPL'01), G. Brebner, and R. Woods (Eds.), Field-Programmable
Logic and Applications 11th International Conference, FPL 2001, Belfast,
Northern Ireland, UK, August 27-29, 2001, Proceedings LNCS (Lecture Notes on
Computer Science) 2147, Springer Verlag, Gordon J. Brebner, Roger Woods
(Eds.), August 2001, pp. 523-533.
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João M. P. Cardoso, and Horácio C. Neto, “Architectural Synthesis
Exposing Parallelism and Increasing the Scheduling Scope for FPGA-based Digital
Systems,” In Proc. of the 5th World Multi-Conference on
Systemics, Cybernetics and Informatics (SCI’01) and the 7th Int.
Conf. on Information Systems Analysis and Synthesis (ISAS’01), July 22-25,
Orlando, Florida, USA, Vol. XI, Information Systems Technology.
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1999 |
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João M. P. Cardoso, and Horácio C. Neto, “An Enhanced Static-List
Scheduling Algorithm for Temporal Partitioning onto RPUs,” In Proc.
of the IFIP TC10 WG10.5 X International Conference on Very Large Scale
Integration (VLSI'99),
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João M. P. Cardoso, and Horácio C. Neto, "Fast Hardware
Compilation of Behaviors into an FPGA-Based Dynamic Reconfigurable Computing
System," In Proceedings of the XII Symposium on Integrated
Circuits and Systems Design (SBCCI’99), Natal-RN, Brazil, Sept. 29-Oct.
2, 1999, Co-Sponsored by the Brazilian Computer Society and the IFIP WG 10.5.
In Vladimir C. Alves, Marcelo Lubaszewski and Ivan S. Silva (Editors), IEEE
Computer Society Press,
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João M. P. Cardoso, and Horácio C. Neto, "Macro-Based
Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable
Computing System," In Proceedings of the 7th IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM'99), Napa Valley,
California, USA, April 21 - 23, 1999, In Kenneth L. Pocek and Jeffrey M. Arnold
(Editors), IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 2-11.
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1998 |
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João M. P. Cardoso, and Horácio C. Neto, "An Approach to
Hardware Synthesis from a System Java(tm) Specification," In the Proceedings
of the 1st International Workshop on Design, Test and Applications (WDTA'98),
Sponsored by IEEE Region 8 and IEEE TTTC,
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João M. P. Cardoso, and Horácio C. Neto, "Towards an
Automatic Path from Java(tm) Bytecodes to Hardware Through High-Level Synthesis,"
In Proceedings of the 5th IEEE International Conference on Electronics,
Circuits and Systems (ICECS'98), Lisbon, Portugal, September 7-10,
1998, pp. 85-88.
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1996 |
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João M. P. Cardoso, and Horácio C. Neto, "A
Parameterizable Processor Core for Fast Turnaround Co-Synthesis of Embedded
Systems,” In Proceedings of the XI SBMicro Conference (SBMICRO’96),
Águas de Lindóia - SP - Brazil , July 29 - August 2, 1996, pp. 16-21.
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João M. P. Cardoso, Horácio C. Neto, "A Co-synthesis
Environment for Embedding Digital Systems in a Sea-of-gates IC,” In Proceedings
of the XI Conference on Design of Integrated Circuits and Systems (DCIS'96),
Sitges (Barcelona), November 19-22, 1996, pp. 411-416.
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Papers
in
Refereed National Conferences |
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Fábio Silva, Milton
Godinho e João M. P. Cardoso, “Sistema Implementado em FPGA para
Reconhecimento de Comandos baseados em Posturas de Mãos,” in REC2006, Jornadas sobre Sistemas
Reconfiguráveis, FEUP, Porto, Portugal, 16-17 Fevereiro 2006.
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João Lima, João M. P.
Cardoso e Eduardo Marques, “Metodologia para Implementação de Controladores
PID em FPGAs,” in REC2006, Jornadas
sobre Sistemas Reconfiguráveis, FEUP, Porto, Portugal, 16-17 Fevereiro
2006.
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Rui F. L. Marcelino, e
João M. P. Cardoso, “An Introduction to Commercial Reconfigurable Processing
Architectures,” in REC2006, Jornadas
sobre Sistemas Reconfiguráveis, FEUP, Porto, Portugal, 16-17 Fevereiro
2006.
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Ricardo Ferreira, João
M. P. Cardoso, and Horácio C. Neto, “EDA: An Environment for Exploring
Data-Driven Architectures,” in Jornadas
sobre Sistemas Reconfiguráveis (REC2005), Universidade do Algarve, Algarve,
February 21 2005, pp.. (extended version of the paper presented at FPL03)
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João M. P. Cardoso, M.
M. Fernandes, Vanderlei Bonato, E. D. V. Simões, Eduardo Marques, “Proposta
de um Ambiente para Codesign de Hardware/Software em Plataformas de FPGAs com
Aplicação em Robótica Móvel,” in Simpósio
Latino Americano em Aplicações de Lógica Programável e Processadores Digitais
de Sinais em Processamento de Vídeo, Visão Computacional e Robótica –
SLALP’2004, Departamento de Engenharia Elétrica, Escola de Engenharia de
São Carlos – USP, São Carlos - SP – Brasil, 8 a 10 de Novembro de 2004.
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João M. P. Cardoso, and Horácio C. Neto, “Compilation of High-Level
Languages onto Fine-Grain FCCMs with Exploitation of Instruction-Level
Parallelism,” In Proc. of the 4th Portuguese
Conference on Automatic Control (CONTROLO'2000), 4-6 October 2000, Guimaraes, Portugal,
special session MESC (Methodologies for the Engineering of Control Systems)
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“Method and
Device for Partitioning Large Computer Programs,”
Patent Number: EP1470478, Publication date: 2004-10-27
Inventor(s): CARDOSO JOAO
(DE); VORBACH MARTIN (DE); WEINHARDT MARKUS (DE). Applicant(s): PACT XPP
TECHNOLOGIES AG (DE).
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“Method for Processing Data”
Patent Number: US2004015899;
Publication Date: 2004-01-22
Inventor(s): MAY FRANK (DE); NUCKEL ARMIN (DE);
VORBACH MARTIN (DE); WEINHARDT MARKUS (DE); CARDOSO JOAO (PT)
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“Method of Compilation”
Patent Number: US2005132344;
Publication Date: 2005-06-16
Patent Number: WO03071418,
Publication date: 2003-08-28
Inventor(s): Cardoso João
(de); Vorbach Martin (de); Weinhardt Markus (de), applicant(s): Cardoso João
(de); Vorbach Martin (de); PACT XPP Technologies AG (de); Weinhardt Markus
(de).
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“Data Processing Method,”
Patent Number: US2004243984;
Publication date: 2004-12-02
Patent Number: EP1402382,
Publication date: 2004-03-31
Inventor(s): MAY FRANK
(DE); NUECKEL ARMIN (DE); VORBACH MARTIN (DE); WEINHARDT MARKUS (DE); CARDOSO
JOAO MANUEL PAIVA (PT). Applicant(s): PACT XPP TECHNOLOGIES AG (DE).
Patent Number: WO02103532,
Publication date: 2002-12-27
Inventor(s): May Frank (de); Nueckel Armin (de);
Vorbach Martin (de); Weinhardt Markus (de); Cardoso Joao (pt). Applicant(s):
May Frank (de); Nueckel Armin (de); Vorbach Martin (de); PACT XPP Technologies
AG (de); Weinhardt Markus (de); Cardoso João (pt):
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“Integrated cell
matrix circuit has at least 2 different types of cells with interconnection
terminals positioned to allow mixing of different cell types within matrix
circuit”
Patent Number: DE10129237,
Publication date: 2002-04-18, Inventor(s): May Frank (de); Nueckel Armin (de);
Vorbach Martin (de); Weinhardt Markus (de); Cardoso João (pt), applicant(s):
PACT Inf Tech Gmbh (de).