CHIADO - Compilation of High-Level Computationally Intensive Algorithms to Dynamically Reconfigurable COmputing Systems

 

[SUMMARY] [KEYWORDS] [PUBLICATIONS]

 

Funded by the Portuguese Foundation for Science and Technology (FCT), POSI and FEDER, POSI/CHS/48018/2002

Starting date: January 5, 2004

Duration: 3 years

Participant Institutions

Team Members

1University of Algarve

Faculty of Sciences and Technology

http://www.ualg.pt

Faro, Portugal

- João M. P. Cardoso1,2 (jmpc@acm.org), Project leader

- Rui Rodrigues1, DEng., full-time researcher

- Rui Marcelino, DEng., MSc, part-time researcher (PhD student)

- Sunil K. Reddy Yerasani1, a BTech. Computer Science & Engineering student from Indian Institute Of Technology, India (internship during 3 months, 2004)

2INESC-ID, http://www.inesc-id.pt

Lisbon, Portugal

- Horácio C. Neto2 (hcn@inesc.pt)

 

Project Summary: Reconfigurable computing (RC) has already confirmed a significant potential for accelerating certain general-purpose computing tasks. Since RC systems are capable to provide a mix of flexibility, high-performance, and low power consumption (when compared to microprocessors and DSPs) their use is increasing. As RC is based on hardware foundations, it inherited its design difficulties. The methods that have been used for the realization of the most successful applications of RC require user's hardware expertise. Today's RC devices, with millions of logic gates, distributed memories and embedded multipliers, are capable to accommodate complex algorithms. Thus, one of the most challenging issues is the methodology to efficiently and automatically map computations (described in software programming languages) to these systems. Moreover, the compiler performance must not be significantly slower than software compilation to a generic processor in order to permit rapid development and evaluation of different high-level decisions (e.g., hardware/software partitioning), both important to deal with time-to-market pressures.

Since the execution on RC systems can be divided in sequential stages (e.g., fetch, configure, and compute) it is important to find, from the input algorithm, the set of configurations that both produces feasible implementations (considering the available number of resources) and minimizes the overall performance. To minimize the performance it is essential to consider the overlapping of the stages related to different configurations. Based on our previous work on temporal partitioning and on the framework already existent, we propose to R&D techniques to map efficiently complex applications to RC systems also considering this form of pipelining. The work includes high-level estimations (resources needed and latency) from the original algorithm and including the impact of some transformations supported by the compiler (partial/full loop unrolling).

In order to provide full support for the design compilation, the work will also include the R&D of module-generators to produce the specific components mainly required to access the memories and to perform the primitive operations used in the Java subset. In parallel to the R&D of mapping methods, two practical benchmarks will be implemented with a traditional design flow in a commercial RC board in order to find efficient hardware techniques and to provide a final evaluation of the results obtained using the compiler.

Keywords: Compilation, Architectural Synthesis, Reconfigurable Computing, Computer Architecture, FPGAs

Publications (some of them have been partially supported by CHIADO):

w         João M. P. Cardoso, “On Estimations for Compiling Software to FPGA-based Systems,” in IEEE 16th International Conference on Application-specific Systems, Architectures and Processors (ASAP’05), Samos, Greece, July 23-25, 2005, IEEE Computer Society Press, pp. 225-230.

w         João M. P. Cardoso, “Dynamic Loop Pipelining in Data-Driven Architectures,” in Proc. of the ACM International Conference on Computing Frontiers (CF’05), Ischia, Italy, 4-6 May 2005, ACM Press, pp. 106-115.

w         João M. P. Cardoso, “CHIADO: compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems,” in SPIE Microtechnologies for the New Millennium 2005 Symposium, Seville, Spain, May 9-11, 2005, SPIE Vol. 5837, pp. 893-901.

w         Rui Rodrigues, and João M. P. Cardoso, “An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs,” Interactive Presentation at the Design, Automation and Test in Europe Conference (DATE’05), Munich, Germany, March 7-11, 2005, IEEE Computer Society Press, pp. (to appear).

w        Ricardo Ferreira, João M. P. Cardoso, and Horácio C. Neto, “An Environment for Exploring Data-Driven Architectures,” in 14th International Conference on Field Programmable Logic and Applications (FPL’04), Antwerp, Belgium, August 30 - September 1, 2004, LNCS 3203, Springer-Verlag, Jürgen Becker, Marco Platzner, Serge Vernalde (eds.), August 2004, pp. 1022-1026.

w        João M. P. Cardoso, and Pedro C. Diniz, “Modeling Loop Unrolling: Approaches and Open Issues,” in International Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS IV), Samos, Greece, July 19-21, 2004. Computer Systems: Architectures, Modeling, and Simulation, LNCS 3133, Springer Verlag, Andy Pimentel and Stamatis Vassiliadis (Eds.), July 2004, pp. 224-233.

w        João M. P. Cardoso, “Self Loop Pipelining and Reconfigurable Dataflow Arrays,” in International Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS IV), Samos, Greece, July 19-21, 2004. Computer Systems: Architectures, Modeling, and Simulation, LNCS 3133, Springer Verlag, Andy Pimentel and Stamatis Vassiliadis (Eds.), July 2004, pp. 234-243.